On Embedded Processor Reconfiguration of Logic Bist for Fpga Cores in Socs

Due to the limited access to the individual embedded cores in System-on-Chips (SoCs), testing is more time consuming and costly than testing standalone Field Programmable Gate Arrays (FPGAs). However, the ability for an embedded processor core to reconfigure FPGA cores in SoC applications opens new opportunities for Built-In Self-Test (BIST) of the FPGA cores themselves. This paper discusses a number of implementation issues in BIST for FPGA cores using partial dynamic reconfiguration from an embedded processor including efficient ordering of the reconfiguration process, actual speed-up and memory savings associated with logic BIST, and the resulting affect on diagnosis of the logic resources in the FPGA core.